Scalable Hardware Efficient Architecture for Parallel FIR Filters with Symmetric Coefficients

Symmetric convolutions can be utilized for potential hardware resource reduction. However, they have not been realized in state-of-the-art transposed block FIR designs. Therefore, we explore the feasibility of symmetric convolution parallel FIRs and propose a scalable efficient architecture. The proposed design inserts delay elements after multipliers temporal reuse intermediate tap products. By doing this, number required reduced by half. As result, achieve up to 3.2× 1.64× area efficiency improvements over modern method on reconfigurable fixed designs, respectively. These results confirm effectiveness STB-FIR architecture hardware-efficient, high-speed signal processing.